A. Field of the Invention
The present invention relates generally to data transfer and, more particularly, to interfaces that enable multiple types of buses over a common physical connection.
B. Description of Related Art
A communications bus can be used to couple electrical components in a network device. One attribute of bus operation is signal timing. In a source synchronous bus, for instance, the bus is driven by a common clock and all signals are sampled based on the common clock. The common clock may be provided by the transmitting component and transmitted with the data. An asynchronous bus does not provide a common timing clock. For an asynchronous bus, the receiving device may generate a clock signal, based on the received data signal, that is then used to sample the data signal.
It can be desirable to include multiple different bus techniques in a single system. For example, a system, such as a router, may include many different interchangeable circuit boards, some of which are designed to communicate with other circuit boards using a source synchronous bus and others of which were designed to communicate via an asynchronous bus. It would be desirable to allow the source synchronous circuit boards and the asynchronous circuit boards to share a common set of bus connection paths. Such a multi-interface bus can be difficult to implement, particularly in high bandwidth applications. In such applications, using quick switches (e.g., FET transistors) and multiplexers to switch between buses can introduce undesirable effects, such as signal skew.
Accordingly, it would be desirable to implement an effective multi-interface high speed bus.